1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of the Related Art
In recent years, a number of semiconductor memory devices in which memory cells are three-dimensionally arranged to increase the degree of integration of memories have been proposed (for example, see Japanese Unexamined Patent Application Publication Nos. 2007-266143 and 2013-4690).
According to one proposal, polysilicon films and silicon oxide films are alternately formed, a memory plug hole for forming a pillar-shaped semiconductor of a memory transistor is then formed, and an amorphous silicon film is deposited in the memory plug hole to form a pillar-shaped amorphous silicon layer. Then photo-etching is performed to isolate the layers of selection gate transistors (for example, see Japanese Unexamined Patent Application Publication No. 2007-266143).
In another proposal, layers of selection gate transistors and word lines are isolated (for example, see Japanese Unexamined Patent Application Publication No. 2013-4690).
In order to form a structure in which a selection gate surrounds a pillar-shaped amorphous silicon layer through a method that includes alternately forming polysilicon films and silicon oxide films, forming a memory plug hole for forming a pillar-shaped semiconductor of a memory transistor, depositing an amorphous silicon film in the memory plug hole to form a pillar-shaped amorphous silicon layer, and then isolating the layer of the selection gate transistor by photo-etching, the photoresist used for isolating the layer of the selection gate transistor needs to cover the pillar-shaped amorphous silicon layer and this requires extra spaces for mask alignment. Accordingly, the area needed for one pillar-shaped amorphous silicon layer is increased.
When amorphous silicon or polycrystalline silicon is used to form a pillar-shaped silicon layer, crystal grain boundaries decrease the charge mobility and the read rate.
In related art, a metal-gate-last process has been employed to form MOS transistors (see IEDM 2007 K. Mistry et. al, pp 247-250). A metal-gate-last process is a process that includes both a metal gate process and a high-temperature process and involves making a metal gate after performing the high-temperature process. According to this method, a gate is made by using polysilicon and then an interlayer insulating film is deposited. The polysilicon gate is exposed by chemical mechanical polishing and etched and then a metal is deposited. In order to use both a metal gate process and a high-temperature process for a SGT, a metal-gate-last process of forming a metal gate after a high-temperature process is desirably employed.
It becomes increasingly difficult to allow an impurity to exist in a silicon pillar as the silicon pillar becomes thinner. This is because density of silicon is 5×1022 atoms/cm3.
According to a proposal related to a SGT, a threshold voltage is determined by changing the work function of a gate material and adjusting the channel density to a level as low as 1017 cm−3 or less (for example, see Japanese Unexamined Patent Application Publication No. 2004-356314).
According to a proposed planar-type MOS transistor, a side wall in the LDD region is formed of polycrystalline silicon having the same conductivity type as that of a low-concentration layer. In this transistor, surface carriers in the LDD region are induced by the difference in work function and the impedance in the LDD region can be decreased compared to an LDD-type MOS transistor with oxide film side walls (for example, see Japanese Unexamined Patent Application Publication No. 11-297984). The polycrystalline silicon side walls are insulated from the gate electrode. The drawings show that the polycrystalline silicon side wall is isolated from the source/drain by an interlayer insulating film.